This invention relates to loop phase detector circuits.
In the operation of the loop phase detector circuits, such as that disclosed in U.S. Pat. No. 3,611,040, there exists the potential of an error being introduced into the circuits that is a consequence of the effects of the temperature of the circuit during operation and/or by fluctuation of the power supply voltages that are connected to the circuit. The prior art provided for minimizing these effects requires double filtering as was used in the circuit provided in FIG. 1 or by special construction of the phase comparator such as that disclosed in U.S. Pat. No. 4,039,967.
Referring to FIG. 1, a loop phase detector circuit consists of a phase comparator circuit 1 which has the advantage of being a commercially available device such as a 2-Input Exclusive "OR" Exclusive "NOR", such as part number MC10107 manufactured by Motorola Corporation, Phoenix, Ariz., and as stated earlier has two input terminals 3 and 5. Connected to terminal 3 is the output frequency of a voltage control oscillator 43 which is fed back to terminal 3 by means of conductor 45. The reference input frequency is connected to terminal 5. The phase comparator circuit 1 provides two outputs which are complementary to each other at terminals 7 and 9, and as indicated by the logic symbol used to denote the comparator 1, the Exclusive "OR" output of the two signals appears on terminal 7 and the Exclusive "NOR" output of the signals appears on terminal 9. The results of the phase comparison is applied to a difference amplifier which has two filters, the first being comprised of resistors 36 and 27 and capacitor 39, and the second filter being comprised of resistors 35 and 29 and capacitor 37. The difference of the voltages that appear on terminal 41 of difference amplifier 30 is used to control the voltage to frequency converter 43 and is the difference of the voltages present on terminals 23 and 25.
Although the circuit of FIG. 1 has been successful in compensating for the effects of the temperatures of the operating circuit and the power fluctuation of the power supplies, it has as a main disadvantage the necessity of providing two loop filters as described in the above discussion.
In addition, the circuit that was disclosed in U.S. Pat. No. 4,039,967 is a complex circuit, and as is obvious from FIGS. 6 and 8 of the patent, requires many additional components than the prior art circuit of FIG. 1 or the circuit as disclosed by the invention.
A loop phase detector circuit in which the phase offset error arising from imperfections in the circuit parameters, inter alia, temperature and power supply voltage, is reduced to a minimum by the circuit arrangement disclosed herein. The phase comparator circuit compares the phase of the output frequency of a voltage to frequency converter with an input reference signal, and provides a phase comparison error signal and the complement of the phase comparison error signal. Due to temperature and supply voltage fluctuation of the circuit, the phase comparison error signal and the complementary phase comparison error signal may not be symmetrical in amplitude and may contain other offset errors not directly related to phase errors. Therefore, the phase comparison error signal is applied to an input of a difference amplifier, and the algebraic sum of the phase comparison error signal and the complementary phase comparison signal is applied to the other input terminal of the difference amplifier, with the result between the two signals being the control voltage for a voltage control oscillator. There is a resistive network which is used to algebraically sum the phase comparison error signal and the complementary phase comparison signal in line between the phase comparison circuit and the difference amplifier which cross couples the phase comparison error signal with the complementary phase comparison error signal, so that fluctuations due to temperature and power supply voltages are drastically reduced.
Many advantages of the present invention may be ascertained from a reading of the specification and the claims in conjunction with the drawings.